FIFO Memories: Solution to Reduce FIFO Metastability First-In, First-Out Technology
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A Low–Latency FIFO for Mixed–Clock Systems∗
This paper presents a low–latency FIFO design that interfaces subsystems on a chip working at different speeds. First, a single-clock domain design is introduced, which is then used as a basis for a mixed–clock version. Finally, the design is adapted to work between subsystems with very long interconnection delays. The designs can be made arbitrarily robust with regard to metastability and cloc...
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تاریخ انتشار 1998